The poor performance characteristics of P channel (PMOS) field effect transistors (FETs) in digital logic applications as compared to N channel (NMOS) FETs is in part due to the mobilities of the respective carriers of the P channel and N channel devices. The carriers of P channel devices are holes, which have a lower mobility than do the electron carriers of N channel devices. P channel devices hence have a higher R.sub.on value than do N channel devices for similar device sizes, indicating that P channel devices have a higher internal resistance during the ON state than do N channel devices. N channel devices also have a narrower channel and take up less space on a semiconductor wafer than do P channel devices. For these reasons, N channel devices are preferred over P channel devices for digital logic applications.
CMOS logic, which is characterized by a logic element formed by the combination of one or more NMOS transistors and one or more complementary PMOS transistors, is preferred for digital applications requiring low power consumption and fast switching between logic states. A logic circuit using only PMOS or only NMOS transistors without its NMOS or PMOS complements, respectively, may draw excessive current in the ON state. CMOS logic devices, in contrast, draw no quiescent current. Also, a logic circuit having only PMOS or NMOS logic may have a high output impedance in the OFF state, a condition which may reduce transistor switching speed. CMOS logic has characteristically low output impedance.
CMOS devices, however, may suffer from high power dissipation at high switching frequencies. The power consumed by a CMOS logic gate increases with increasing switching speed, rendering CMOS logic applications unattractive at high switching speeds. In addition, in a logic circuit having a large number of CMOS gates, each CMOS gate must drive the immediately succeeding gates and therefore encounters the capacitive loading of the succeeding gates. In addition, because a PMOS device has a wider channel and is larger than its N channel complement, the capacitive loading experienced by each CMOS gate is exacerbated by the presence of the PMOS transistor complement of each CMOS logic gate. Therefore, for circuits having high switching speeds, CMOS circuits may not be preferable.
In applications such as busses with several drivers, implementing full CMOS would require considerable wiring resources. The circuit described here would be advantageous in such a case.